The present invention relates to an information processing apparatus for executing a plurality of instructions in parallel and, particularly, to an information processing apparatus suitable for executing a plurality of instructions in a parallel in pipeline mode.
In an information processing system intended to speed up the processing by executing a plurality of instructions in parallel (in this specification, term "parallel" includes partial overlap), e.g., a so-called pipeline processing system, if an instruction for reading out an operand (storage operand) in a certain address of the main storage is preceded by an instruction for writing an operand to that address, the state of so-called operand store conflict in which the following read instruction has the same storage operand as that of the preceding write instruction exists, and the following read instruction exists cannot be executed until the preceding write instruction has been completed. This hampers the progress of processing, and the speed-up of the processing by parallel instruction execution cannot be achieved. One of the conventional countermeasures for this problem is to take out the operand of the preceding write instruction during its execution as the operand of the read instruction. For example, United State patent application Ser. No. 627,922 or Japanese Laid-Open Patent Application No. 60-15746 of the same assignee as the present invention discloses a technique of taking out the operand for the read instruction from the work register which holds temporarily the output of the arithmetic unit.
However, the above-mentioned technique requires work registers and its control circuit. Furthermore, in the above technique, the use of the work register is limited to the case in which the read instruction is executed immediately after the preceding write instruction. Therefore, it is desired to speed up the parallel processing for the case of executing another instruction between the preceding write instruction and the following read instruction.
An example of the preceding write instruction used in the above-mentioned patent application is the instruction for reading out an operand from the main storage, implementing the operation for the operand and writing the result into the main storage, as seen in decimal operation instructions. Another example of instructions for writing an operand into the main storage is the store instruction which writes an operand held by general purpose register (register operand) into the main storage without operation. Conventionally, also in the case of this instruction, a register operand is treated to bypass the arithmetical or logical operation unit (ALU) and is written in the main storage.